The subject matter disclosed herein relates to the analysis of integrated circuits, logic gates and/or multi-finger semiconductor devices, such as multi-finger metal-oxide-semiconductor (MOS) transistors, multi-finger MOS capacitors, etc. Specifically, the subject matter disclosed herein relates to solutions for netlist reductions of a multi-finger device.
The design process for a semiconductor device, a logic gate or an integrated circuit may include computer implemented transistor-level circuit layout simulations. These simulations may include a Simulation Program with Integrated Circuit Emphasis (SPICE) netlist which includes the parasitic resistive elements (e.g., diffusion resistance, contact resistances, local wire resistance, etc.), parasitic capacitive elements (capacitive coupling between a transistor's gate and source, capacitive coupling between a transistor's gate and drain, capacitive coupling between a transistor's source and drain, etc.), and parasitic inductive elements, which are inherent in semiconductor devices and circuits. Values (e.g., resistance, capacitance, inductance, etc.) for these parasitic elements may be extracted from a design layout by a parasitic extraction tool and included in the netlist before simulation (e.g. a SPICE simulation) of the design, thereby allowing for the effects of these parasitic elements to be accounted for in the simulation results. However, inclusion of parasitic elements in the netlist may increase the processing time and computation cost associated with the simulation, thereby complicating the design and simulation process. While some netlist elements (e.g., interconnect resistive elements and interconnect capacitive elements) can be reduced using approaches known in the art (e.g., Δ-Y transformation or delta-star transformation, filtering, delay-oriented local operations, mathematical model order reduction, etc.), a netlist for multi-finger devices is difficult to effectively reduce, as it contains a netlisting of multiple MOS transistors (i.e., multiple model calls of MOS transistors).